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    Boncoin - Capijob

    Boncoin - Capijob

    Junior Analog Layout Engineer (f/m)

    Dpt / Région : Provence Alpes Côte d'Azur, 05, 06, 13, 83, 84, 04

    Contrat :

    Expérience : NC

    Niveau d´étude : NC

    Permis demandé : Permis NC

    Salaire :

    Niveau de qualification : NC

    Société : nxp semiconductors


    The business line Advance Automotive Analog develops highly integrated solutions for the automotive industry. The Layout engineering team based in Toulouse is delivering SoC layouts to multiple product lines addressing the automotive and industrial applications.

    Job Summary

    We are looking for an IC Analog layout engineer to work with our product organizations to define and develop the next generation of Battery Management System IPs and products within BL AA.

    The candidate must have knowledge of Analog layout tools and methodologies used in all layout design phases. The candidate will be part of the team and deliver major contributions at both top and block level of the products.

    As a member of the team, you will be responsible for

    • Delivering floorplan activities at IP level
    • Participating to the power supply strategy, signals distribution between blocks
    • Delivering Analog layout blocks
    • Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries
    • Participating to design reviews, write documentation and support for integration into products
    • Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect)

    Your Profile

    • ~3 years of experience in Analog layout design
    • Fluent in English
    • Good expertise in Analog layouts, device physics and IC ESD protection strategies
    • knowledge in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre)
    • Ability to collaborate with experienced people having different technical profiles
    • Knowledge in physical implementation in Analog blocks at IPs and/or SOC level
    • Ability to leverage his expertise to provide training, support and write guidelines focused on layout activities